Library ieee;
Use ieee.std_logic_1164.ALL;
Use ieee.std_logic_unsigned.ALL;

Entity k1 is
 port(led: out std_logic_vector(3 downto 0);
      clk: in std_logic);
end;

Architecture rtl of k1 is
signal count: std_logic_vector(25 downto 0);
begin
 led <= count(25 downto 22);

 process(clk)
 begin
  if clk'event and clk='1' then
   count <= count+1;
  end if;
 end process;

end;