pekdb XC9572 Experiment Board

About
Experiment with Xilinx CPLDs. On this simple board XC9572 is mounted in the PLCC44 socket. The crystal oscillator is mounted in a DIL8 socket and can easy be changed to give an appropriate clock signal.




Programming
To program the CPLD you need a programmer with JTAG interface. Xilinx has a circuit diagram of a buffered programmer on their homepage. But an even more simpler programmer can be built with only two connectors and one resistor. To read more about it, visit Cheaptag.

For the Cheaptag programming cable to be compatible with the JTAG connector of the experiment board you need to build it right. Click here to see the design of the cable. The length of the cable is very critical. Do not use a cable longer than 50 cm, or you may have some problems with the communication.

From the beginning the Cheaptag cable above worked well. After some time it didn't work at all, tried on three computers! Xilinx Impact couldn't identify the CPLD circuit and the message unknown device appeared all the time. I tried to figure out what was wrong and came out with a new modified schematic of the cable. The changes against Cheaptag that was done before the cable started to work were a buffered TCK signal and a small capacitance between TDO and ground. Click here to look at the finnished circuit diagram.

The software needed for synthetizing, place & route and programming is Xilinx Webpack. It can be downloaded from Xilinx homepage.

Use Impact from Xilinx Webpack to program the CPLD device. After installing you don't need to do any settings, only let Impact automatically scan for the parallel cable in boundary scan mode.
When you run Impact this window appears. Choose Configure Devices and press Next.
Choose Boundary-Scan Mode and press Next.
Choose Automatically connect to cable and identify Boundary-Scan chain and press Next.
If everything works well you'll now see that the Xilinx device is identified (xc9572) and the program asks for a jedic file. The jedic file contains information about the CPLD device and the code to download. Select your jedic file.
Click on the CPLD device in the chain above and choose Program in the Operations menu. Choose Erase Before Programming and Verify before you press OK.

Maybe you are looking for a VHDL example to verify the Experiment board and the Programming cable. Download this simple counter, program the CPLD device with the Jedic file, mount a 50 MHz crystal oscillator and look at the leds on the experiment board.

Click here to download Jedic file.
Click here to download VHDL file.


Design
Click here to see the circuit diagram.
Click here to see the pcb layout.
Click here to see the component layout.
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