PLL and 16 MHz crystal for USB
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Figure, ch 25.4 (Divider and PLL Block)

Filter for PLL:

R=390
C1=10nF
C2=1nF

DIV = 1
MUL = 6

Set the clock:

// Enable Main Oscillator
// Main Oscillator Startup Time set to 2 ms
// (0x08 for AT91C_CKGR_OSCOUNT field)
AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (0x8 << 8)) | AT91C_CKGR_MOSCEN;

// Wait until the oscillator is stabilized
while (!ISSET(AT91C_BASE_PMC->PMC_SR, AT91C_PMC_MOSCS));

// Set PLL to 96MHz (96=16/1*(5+1)) and UDP Clock to 48MHz
// PLL Startup time depends on PLL RC filter
AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | AT91C_CKGR_OUT_0 | (AT91C_CKGR_PLLCOUNT & (0x30 << 8)) | (AT91C_CKGR_MUL & (5 << 16)) | (AT91C_CKGR_DIV & 1);

// Wait until the PLL is stabilized
while(!ISSET(AT91C_BASE_PMC->PMC_SR, AT91C_PMC_LOCK));

// Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
// The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
while (!ISSET(AT91C_BASE_PMC->PMC_SR, AT91C_PMC_MCKRDY));

SET(AT91C_BASE_PMC->PMC_MCKR, AT91C_PMC_CSS_PLL_CLK);
while (!ISSET(AT91C_BASE_PMC->PMC_SR, AT91C_PMC_MCKRDY));